Most current-generation dynamic random access memory circuits comprise arrays of memory cells, each memory cell containing two main components: a field effect transistor and a capacitor. Broadly speaking, the transistor acts like a switch and the capacitor acts like a storage battery. When switched on, the transistor supplies a current which charges the capacitor. The charge stored in the capacitor is then used to represent a data value.
Because the charge stored in the capacitor represents a data value, the capacitor must be able to store a certain minimum charge to ensure reliable operation of the memory cell. With recent advances in the miniaturization of integrated circuits, however, it has become more difficult to build capacitors large enough to store such a minimum charge. Consequently, manufacturers of dynamic random access memory circuits have attempted to increase the total charge capacity of a memory cell capacitor without significantly affecting the chip area occupied by the memory cell. Such techniques concentrate on increasing the effective surface area of the capacitor by creating three-dimensional structures which increase the effective surface area of the capacitor while better utilizing available space.
One method of increasing a capacitor's storage size in densely packed memory devices is to use "stacked capacitor" designs. Stacked capacitor designs use the space existing over the memory cell to create a high-aspect-ratio, three-dimensional capacitor. For example, stacked capacitor designs can include container-within-container structures or multiple cylindrical structures. Fabrication of such structures, however, requires a variety of complex processes, including multiple mask, deposition, and etching steps.
For instance, a paper submitted by J. H. Ahn, et al., entitled "Micro Villus Patterning (MVP) Technology for 256 MbDRAM Stack Cell," 1992 IEEE, 1992 Symposium on VLSI Technology Digest of Technical Papers, pp. 12-13, which is hereby incorporated herein by reference, discusses micro villus patterning technology to develop a three-dimensional stacked capacitor having villus bars. This micro villus patterning technology, however, may result in splintering or slivering problems.
For example, the three-dimensional villus bars may deform or splinter creating a short in an adjacent memory cell, which renders the adjacent memory cell unusable. Furthermore, when using a spherical-grain polysilicon, the variable grain sizes can produce structures having diameters smaller than 0.010 micrometers. Consequently, such structures are more susceptible to breaking and splintering. U.S. Pat. No. 5,340,763, issued Aug. 23, 1994 to Dennison, which is hereby incorporated herein by reference, discloses one method of forming stacked capacitors while minimizing or containing the damage caused by such breakage.
Furthermore, the three-dimensional capacitor structures are more susceptible to breakage during particular processing steps. In general, three-dimensional capacitor structures include a bottom electrode layer, a dielectric layer and a top electrode layer. The bottom electrode layer is formed within what is called a "sacrificial mould." The sacrificial mould (or mold) is a structural layer which provides support for and defines the shape of the bottom electrode layer.
Once the sacrificial mold is removed, such as during a wet etch process step, a dielectric layer and a second electrode layer are then deposited onto the three-dimensional electrode. Thus, after the removal of the sacrificial mold, the fragile three-dimensional bottom electrode layer is exposed until the deposition of the dielectric layer and top electrode. As a result, the bottom electrode layer often breaks and splinters when subjected to external vibrations and forces.
Furthermore, in conventional systems, at the end of a wet etching step, the memory cells are spin dried in a centrifuge. The resulting centrifugal forces placed on the memory cell tends to further break and damage the exposed electrode layer. In addition, inter-chamber transportation of the exposed electrode layer from the wet etch process step to the dielectric deposition step can subject the exposed electrode layer to external vibrations which further damage and break the fragile structure of the electrode.
Accordingly, manufacturers of three-dimensional stacked capacitors need a cost-effective and delicate system which reduces the amount of breakage and splintering which occurs when forming three-dimensional stacked capacitors.